V2 z114 z196 LPAR MF LPAR RNI and Cache

CA MICS Hardware and SCP Analyzer (RMF) Queries › Hardware Instrumentation Services CPU Measurement Facility › RMFWCL - CPU MF Workload Characterization LPAR Level › Data Extracts › V2 z114 z196 LPAR MF LPAR RNI and Cache

V2 z114 z196 LPAR MF LPAR RNI and Cache

VIEW 1 of 7: V2 z114 z196 LPAR – RNI Workload Hint and L1 Cache Miss Pct
Left Y axis: Workload Hint (Low-1 Avg-2 High-3)
CML2RNI – V1 Relative Nest Intensity
CMLPCL1M – Pct Level 1 Cache Miss
Workload Hint Reference Area – shaded gray from 1-3
X axis: DATEHHMM – Date: Hour : Minute
VIEW 2 of 7: V2 z114 z196 LPAR – L1 Cache Miss Sourcing Percentages
Left Y axis: CML2PC15 – V2 PCT L1 from L2
CML2PC3A – V2 PCT L1 from L3 On-Bk On-Chp
CML2PC3B – V2 PCT L1 from L3 On-Bk Off-Chp
CML2PC4A – V2 PCT L1 from L4 On-Bk
CML2PC4B – V2 PCT L1 from L4 Off-Bk
CML2PC5A – V2 PCT L1 from Local Memory
CML2PC5B – V2 PCT L1 from Remote Memory
Right Y axis: AVGPCBSY – Avg IPU Busy for LPAR
CMLPCL1M – Pct Level 1 Cache Miss
X axis: DATEHHMM – Date: Hour : Minute
VIEW 3 of 7: V2 z114 z196 LPAR – L1 Data Cache Miss Sourcing Percentage

V1 z114 z196 LPAR – L1 Data Cache Miss Sourcing Percentages

Left Y axis: CML2PD15 – V2 PCT L1-D from L2
CML2PD3A – V2 PCT L1-D from L3 On-Bk On-Chp
CML2PD3B – V2 PCT L1-D from L3 On-Bk Off-Chp
CML2PD4A – V2 PCT L1-D from L4 On-Bk
CML2PD4B – V2 PCT L1-D from L4 Off-Bk
CML2PD5A – V2 PCT L1-D from Local Memory
CML2PD5B – V2 PCT L1-D from Remote Memory
Right Y axis: AVGPCBSY – Avg IPU Busy for LPAR
CMLPCL1M – Pct Level 1 Cache Miss
X axis: DATEHHMM – Date: Hour : Minute
VIEW 4 of 7: V2 z114 z196 LPAR – L1 Instruction Cache Miss Sourcing Percentages
Left Y axis: CML2PI15 – V2 PCT L1-I from L2
CML2PI3A – V2 PCT L1-I from L3 On-Bk On-Chp
CML2PI3B – V2 PCT L1-I from L3 On-Bk Off-Chp
CML2PI4A – V2 PCT L1-I from L4 On-Bk
CML2PI4B – V2 PCT L1-I from L4 Off-Bk
CML2PI5A – V2 PCT L1-I from Local Memory
CML2PI5B – V2 PCT L1-I from Remote Memory
Right Y axis: AVGPCBSY – Avg IPU Busy for LPAR
CMLPCL1M – Pct Level 1 Cache Miss
X axis: DATEHHMM – Date: Hour : Minute
VIEW 5 of 7: V2 z114 z196 LPAR Penalty Cycles and Avg Penalty per L1 Miss
Left Y axis: CMLB3 – Total L1 I-Cache Penalty Cycles
CMLB5 – Total L1 D-Cache Penalty Cycles
Right Y axis: CML2AVPM – V2 Avg Penalty Cycles per L1 Miss
CML2AVPD – V2 Avg Penalty Cycles per L1 D-Miss
CML2AVPI – V2 Avg Penalty Cycles per L1 I-Miss
X axis: DATEHHMM – Date: Hour : Minute
VIEW 6 of 7: V2 z114 z196 LPAR – Realized MIPS and Avg IPU Count
Left Y axis: CMLMIPS – Actual MIPS Usage Rate
Right Y axis: CMLAVIPU – Average Processor Count
X axis: DATEHHMM – Date: Hour : Minute
VIEW 7 of 7: V2 z114 z196 LPAR – Instruction Count and CPI

Left Y axis: CMLP33 – P33-ProbSt Instructions
CMLS33 – SuperV-State Instructions
Right Y axis: CMLCPI – Cycles per Instrucion
CPI_P – Cycles per Instruction Problem State
CPI_S – Cycles per Instruction Supervisor State
X axis: DATEHHMM – Date: Hour : Minute