CA MICS Hardware and SCP Analyzer (RMF) Queries › Hardware Instrumentation Services CPU Measurement Facility › RMFWCL - CPU MF Workload Characterization LPAR Level › Data Extracts › V3 zEC12 MF LPAR RNI and Cache

V3 zEC12 MF LPAR RNI and Cache

VIEW 1 of 7: V3 zEC12 LPAR – RNI Workload Hint and L1 Cache Miss Pct

Left Y axis

Vx Workload Hint

CMLxRNI – Vx Relative Nest Intensity

CMLPCL1M – Pct Level 1 Cache Miss

Workload Hint Reference Area – (Low-1 Avg-2 High-3) shaded gray from 1-3

where “x” is “2” for V2 (z114, z196) charts, “3” for V3 (zEC12) charts

X axis

DATEHHMM – Date: Hour : Minute

VIEW 2 of 7: V3 zEC12 LPAR – L1 Cache Miss Sourcing Percentages

Left Y axis

CMLxPC15 – Vx PCT L1 from L2

CMLxPC3A – Vx PCT L1 from L3 On-Bk On-Chp

CMLxPC3B – Vx PCT L1 from L3 On-Bk Off-Chp

CMLxPC4A – Vx PCT L1 from L4 On-Bk

CMLxPC4B – Vx PCT L1 from L4 Off-Bk

CMLxPC5A – Vx PCT L1 from Local Memory

CMLxPC5B – Vx PCT L1 from Remote Memory

where “x” is “2” for V2 (z114, z196) charts, “3” for V3 (zEC12) charts

Right Y axis

AVGPCBSY – Avg IPU Busy for LPAR

CMLPCL1M – Pct Level 1 Cache Miss

X axis

DATEHHMM – Date: Hour : Minute

VIEW 3 of 7: V3 zEC12 LPAR – L1 Data Cache Miss Sourcing Percentage

Left Y axis

CMLxPD15 – Vx PCT L1-D from L2

CMLxPD3A – Vx PCT L1-D from L3 On-Bk On-Chp

CMLxPD3B – Vx PCT L1-D from L3 On-Bk Off-Chp

CMLxPD4A – Vx PCT L1-D from L4 On-Bk

CMLxPD4B – Vx PCT L1-D from L4 Off-Bk

CMLxPD5A – Vx PCT L1-D from Local Memory

CMLxPD5B – Vx PCT L1-D from Remote Memory

where “x” is “2” for V2 (z114, z196) charts, “3” for V3 (zEC12) charts

Right Y axis

AVGPCBSY – Avg IPU Busy for LPAR

CMLPCL1M – Pct Level 1 Cache Miss

X axis

DATEHHMM – Date: Hour : Minute

VIEW 4 of 7: V3 zEC12 LPAR – L1 Instruction Cache Miss Sourcing Percentages

Left Y axis

CMLxPI15 – Vx PCT L1-I from L2

CMLxPI3A – Vx PCT L1-I from L3 On-Bk On-Chp

CMLxPI3B – Vx PCT L1-I from L3 On-Bk Off-Chp

CMLxPI4A – Vx PCT L1-I from L4 On-Bk

CMLxPI4B – Vx PCT L1-I from L4 Off-Bk

CMLxPI5A – Vx PCT L1-I from Local Memory

CMLxPI5B – Vx PCT L1-I from Remote Memory

where “x” is “2” for V2 (z114, z196) charts, “3” for V3 (zEC12) charts

Right Y axis

AVGPCBSY – Avg IPU Busy for LPAR

CMLPCL1M – Pct Level 1 Cache Miss

X axis

DATEHHMM – Date: Hour : Minute

VIEW 5 of 7: V3 zEC12 LPAR Penalty Cycles and Avg Penalty per L1 Miss

Left Y axis

CMLB3 – Total L1 I-Cache Penalty Cycles

CMLB5 – Total L1 D-Cache Penalty Cycles

Right Y axis

CMLxAVPM – Vx Avg Penalty Cycles per L1 Miss

CMLxAVPD – Vx Avg Penalty Cycles per L1 D-Miss

CMLxAVPI – Vx Avg Penalty Cycles per L1 I-Miss

where “x” is “2” for V2 (z114, z196) charts, “3” for V3 (zEC12) charts

X axis

DATEHHMM – Date: Hour : Minute

VIEW 6 of 7: V3 zEC12 LPAR – Realized MIPS and Avg IPU Count

Left Y axis

CMLMIPS – Actual MIPS Usage Rate

Right Y axis

CMLAVIPU – Average Processor Count

X axis

DATEHHMM – Date: Hour : Minute

VIEW 7 of 7: V3 zEC12 LPAR – Instruction Count and CPI

Left Y axis

CMLP33 – P33-ProbSt Instructions

CMLS33 – SuperV-State Instructions

Right Y axis

CMLCPI – Cycles per Instrucion

CPI_P – Cycles per Instruction Problem State

CPI_S – Cycles per Instruction Supervisor State

X axis

DATEHHMM – Date: Hour : Minute