CA MICS Hardware and SCP Analyzer (RMF) Queries › Hardware Instrumentation Services CPU Measurement Facility › RMFWCE - CPU MF Workload Characterization IPU Level › Overview

Overview

The RMFWCE query produces charts that reveal how efficiently workloads executed on each active logical IPU (Individual Processor Unit), assigned to z/OS LPARs, make use of the cache and memory hierarchy of IBM z10 and later generation Central Processing Complexes (CPCs).

The three data extract CSV’s generated by the RMFWCE query are:

• V1 z10 CPU MF IPU RNI and Cache
• V2 z114 z196 CPU MF IPU RNI and Cache
• V3 zEC12 CPU MF IPU RNI and Cache

Each data extract generates the following seven chart views:

1. IPU Level – RNI Workload Hint and L1 Cache Miss Pct
2. IPU Level – L1 Cache Miss Sourcing Percentages
3. IPU Level – L1 Data Cache Miss Sourcing Percentages
4. IPU Level – L1 Instruction Cache Miss Sourcing Percentages
5. IPU Level – Penalty Cycles and Avg Penalty per L1 Miss
6. IPU Level – Realized MIPS and Avg IPU Count
7. IPU Level – Instruction Count and CPI

Refer to the RMFWCL – CPU MF Workload Characterization LPAR Level query description for information about each of these chart views. The only difference between the charts created by the RMFWCL LPAR level query and this RMFWCE IPU level query is one of granularity. Where the RMFWCL query views generate a single chart for each LPAR, the RMFWCE IPU level query views generate a separate chart for each active logical IPU (engine) assigned to each LPAR.

The first chart sample above shows the chart generated for view 1 – RNI Workload Hint and L1 Cache Miss Pct, for a single logical processor assigned to LPAR, ‘CA11.’ LPAR ‘CA11’ is a z/OS LPAR running on an IBM 2817-615 (z196 CPC with 15 CP engines). LPAR ‘CA11’ is defined with four logical CP engines and two logical zIIP engines. The workload hint, Level 1 cache miss percent, and Relative Nest Intensity (RNI) for the zIIP engine with logical IPU address 5 is shown with this chart. There is a large spike in the Level 1 cache miss percentage, and workload hint at about 2 AM.

The second chart sample above shows View 2 – L1 Cache Miss Sourcing Percentages for the same logical engine. You can see that around 2 AM, the IPU busy percentage spiked, and a much greater percentage of Level 1 cache misses were satisfied from the Level 3 On-Book On-Chip cache than normal.