2. PERFORMANCE REPORTING ANALYSIS › 2.4 I/O Configuration Analysis › 2.4.8 FICON Channel Performance Analysis Inquiry › 2.4.8.1 Standard Output › 2.4.8.1.1 Processor Complex & Channel Configuration Report

2.4.8.1.1 Processor Complex & Channel Configuration Report

The Processor Complex & Channel Configuration report provides
a listing of all CECs, LPARs and related FICON channel
definitions for the input data.  This report can be used to
determine the identity of the CECs for later use in data
filtering and to better understand which channels are both
defined and active on their respective LPARs.

                                        CA MICS Performance Manager                                        1
                                    FICON Channel Performance Analysis
                            Processor Complex and Channel Configuration Report
                                        For Monday, August 30, yyyy
 
CEC Serial: 0851 Processor Type: 2084 Model: 307
 
      LCSS: 0    CA11 CA31 CA71  n/a  n/a  n/a XAD1 XAE1 XAT1 XA55 XE21 XE44 XE61  n/a  n/a
 
  Channels:
   41 FC_S         Y    Y    Y    *    *    *    Y    Y    Y    Y    Y    Y    Y    *    *
   42 FC_S         Y    Y    Y    *    *    *    Y    Y    Y    Y    Y    Y    Y    *    *
   43 FC_S         Y    Y    Y    *    *    *    Y    Y    Y    Y    Y    Y    Y    *    *
   44 FC_S         Y    Y    Y    *    *    *    Y    Y    Y    Y    Y    Y    Y    *    *
   45 FC_S         N    N    N    *    *    *    N    N    N    N    N    N    N    *    *

    A 'Y' value indicates that a channel is defined and active.
    A 'N' value indicates that a channel is defined but inactive.
    A '*' value indicates that a channel is undefined


 2-86B  Processor Complex & Channel Configuration report


The Processor Complex and Channel Configuration report is
created by the FICON Channel Performance Analysis query.
This report is a listing of all CECs (PR/SM LPAR Central
Complex) and their respective LPARs that were located within
the input data.  Additionally, for each LCSS within each CEC,
all FICON channels detected are mapped against their
associated LPAR and displayed accordingly.

The fields in the above report include:

CEC Serial   The low-order four bytes of the PRSMCEC data
             element.  This identifies a particular processor
             complex whose channel data is being analyzed.

LCSS         The Logical Channel Subsystem ID.  This one byte
             field, with a range of values from 0-3,
             represents a logical grouping of 256 channels.
             This field is also refered to as the CSSID
             (Channel Sub-system ID).

Note         On the same report row as LCSS are listed the
             LPARs being analyzed within the query.  Any MVS
             image executing under VM, or any non-MVS image
             detected will be excluded, as valid RMF
             measurement data will not be available.

Processor    The model family of the Processor Complex under
Type         study.  This value is obtained from CA MICS data
             element CPUMOD (Processor Model Family).

Model        The model description of the Processor Complex,
             including the model number, derived from data
             element CPCMODID (CPC Model Identifier).

Channels     A composite of two separate data elements: CHPID
             (Channel Path ID) and PCAACRNM (Channel Path
             Acronym).  This field will identify each channel
             being analyzed and also explain the usage of the
             channel; for example, undefined; switched, or
             basic modes.