6. DATA SOURCES › 6.8 PR/SM LPAR Concepts › 6.8.4 Interpreting PR/SM Data › 6.8.4.3 Logical Partition Interaction › 6.8.4.3.2 Logical Processor Dispatching and Execution Rate

6.8.4.3.2 Logical Processor Dispatching and Execution Rate

Modern processors have a special high-speed memory cache that
allows the fetching of instructions and operands much more
quickly than is possible from main memory.  A cache
management algorithm analyzes memory accesses and attempts to
satisfy a significant proportion of future memory accesses
from the cache rather than from main memory.  When the cache
is empty, it takes time for the cache manager to analyze
access patterns and fill the cache.  During this period, the
processor is effectively slowed because instructions and
operands are fetched from main memory, which takes more
machine cycles than fetching from cache.

Each time a central processor is redispatched as a logical
processor, the cache is effectively empty because the
contents do not reflect recent memory accesses.  If the
number of processor dispatches were known, it would be
possible to estimate the effect on processor speed.