6. DATA SOURCES › 6.4 CPU Time Measurements › 6.4.4 Variability in CPU Time › 6.4.4.1 Hardware and Buffer Effects

6.4.4.1 Hardware and Buffer Effects

There are three types of potential delay that depend on
special equipment that may or may not be installed on the
system under study.

The translation-lookaside buffer (TLB) is a part of the
Dynamic Address Translation (DAT) facility that supports
virtual addressing.  The TLB is a special register that
facilitates the conversion of virtual to real addresses.  The
TLB strategy depends upon the assumption that significant
amounts of processing proceed sequentially along a range of
instructions stored in contiguous locations.  Large amounts
of branching within a task or context switching between tasks
will reduce the effectiveness of the TLB.  If the TLB is less
effective, then the processor will accomplish less per unit
time.

One or more High Speed Buffers (caches) may support the
central processor.  The cache operates at a higher speed than
the system's addressable main storage and contains a copy of
a segment of main storage for rapid reference by the
processor.  Cache management algorithms assume that
processing will tend to access contiguous locations in
storage.  Varying amounts of contention for the cache will
lead to varying amounts of work done per unit processor time.
Also, be aware that the hardware may disable the cache if
certain errors are detected, and the disablement may or may
not be reported in SYS1.LOGREC.

CPU upgrades can produce variations in the CPU time captured
in satisfying I/O requests.  The tendency has been to move
the I/O processing responsibilities from the main CPU to the
channels.  The CPU time captured for I/O activity can
vary with different processor configurations.